Damascene processing is a method for forming metal lines on integrated circuits. It involves formation of inlaid metal lines in trenches and vias formed in a dielectric layer (inter metal dielectric). Damascene processing is often a preferred method because it requires fewer processing steps than other methods and offers a higher yield. It is also particularly well-suited to metals such as copper that cannot be readily patterned by plasma etching.
In a typical Damascene process flow, metal (such as copper) is deposited onto a patterned dielectric to fill the vias and trenches formed in the dielectric layer. The resulting metallization layer is typically formed either directly on a layer carrying active devices or on another metallization layer. A stack of several metallization layers can be formed by Damascene processing. The metal-filled lines of this stack serve as conducting paths of an integrated circuit.
Before the metal is deposited into the vias and trenches, the patterned dielectric layer is lined with a thin layer of diffusion barrier material (e.g., Ta, TaNx, or Ta/TaNx bi-layer), and, subsequently, with a thin layer of seed layer material (e.g., Cu or copper alloy). The diffusion barrier layer protects inter-metal dielectric (IMD) and active devices from diffusion of copper and other readily diffusing metals into these regions. The seed layer facilitates deposition of metal into the vias and trenches. For example, in a typical process, a TaNx/Ta diffusion barrier bi-layer is deposited onto a patterned dielectric by physical vapor deposition (PVD), followed by deposition of a thin copper seed layer also by PVD. The partially fabricated IC device is then transferred to an electrofill apparatus, where the seed layer serves as a cathode during electrodeposition, and where the vias and trenches are filled with copper.
The ongoing miniaturization of IC devices demands superior electrical properties from both the dielectric and conductive materials used in IC fabrication. As the features of IC devices continue to shrink, it becomes more common to use dielectrics with very low dielectric constants (k). The low-k dielectric materials used in IC fabrication include carbon doped silicon dioxide, hydrogenated silicon oxycarbides (SiCOH), fluorine doped silicon dioxide, and organic-containing low-k dielectrics. These materials, due to their low dielectric constants, provide low parasitic capacitance and minimize the “crosstalk” between the interconnects in an integrated circuit.